(a) Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and more particularly to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure.
(b) Description of the Related Art
Recently, in the field of analog circuit requiring a high speed operation, semiconductor devices for realizing high capacitance have been developed. In general, since an upper electrode and a lower electrode of a capacitor are made of a conductive polysilicon in a case where the capacitor has a PIP structure where a polysilicon, an insulator, and a polysilicon are stacked in order, a natural oxide film is formed by an oxidation reaction at an interface between the upper and lower electrodes and a dielectric film, which results in reduction of the total capacitance.
To overcome this problem, the structure of capacitor has been changed to a metal/insulator/silicon (MIS) structure or a metal/insulator/metal (MIM) structure. Of these structures, since a capacitor of the MIM structure has a low specific resistance and no inner parasitic capacitance due to depletion, it is mainly used for high performance semiconductor devices.
Conventional techniques for a method for fabricating a thin film capacitor of the MIM structure are disclosed in U.S. Pat. Nos. 6,436,787, 6,426,250, 6,387,775, 6,271,084, and 6,159,793.
Hereinafter, a conventional method for fabricating a thin film capacitor of the MIM structure will be in brief described. FIG. 1 is a sectional view showing a thin film capacitor of a conventional MIM structure.
In order to fabricate the thin film capacitor of the MIM structure shown in FIG. 1, typical processes for fabricating a semiconductor device are first performed on a semiconductor substrate 1, and then a lower insulation film 2 is formed on the semiconductor substrate 1.
Next, a lower metal wire 3, a dielectric layer 4 and an upper metal wire 5 are formed in order on the lower insulation film 2.
Here, the lower metal wire 3 and the upper metal wire 5 correspond to first and second electrode layer layers, respectively, in the MIM capacitor.
Next, the upper metal wire 5 is selectively etched leaving a predetermined width, and then the dielectric layer 4 and the lower metal wire 3 is selectively etched leaving a predetermined width.
In the conventional MIM capacitor as described above, electrostatic capacity depends on a size of the upper metal wire 5.
However, as a size of device becomes reduced due to high integration of semiconductor devices, an area of the upper metal wire becomes smaller. Accordingly, there have been proposed various methods for reducing a thickness of the dielectric layer or increasing a contact area between metals while reducing an overall area without any reduction of electrostatic capacity. These methods are designed for improvement of an operation speed by increasing a coupling ratio in order to secure the electrostatic capacity.
However, with the methods for increasing the coupling ratio, there is a limit to reduction of the upper metal wire while maintaining the electrostatic capacity. Accordingly, there is a keen need for a new method.